1. Field of the Invention
The present invention generally relates to a semiconductor device and an integrated circuit chip (IC chip), and in particular, to a laterally diffused metal oxide semiconductor (LDMOS) device and an IC chip including the same.
2. Description of Related Art
Laterally diffused metal oxide semiconductor (LDMOS) is a power source device commonly used in semiconductor processes. The LDMOS can provide a higher breakdown voltage (Vbd) and has a lower on-resistance (Ron) during operation. Hence, the LDMOS is normally used as a high voltage (HV) device in power management IC (PMIC). The CMOS-DMOS device (CDMOS) process and the HV LDMOS analog process are the process platform for the power management IC.
A conventional PMIC involves HVPMOS and LDNMOS therein. Owing to drain/source on-resistance (Rdson) of the HVPMOS being 3-4 times higher than that of the LDNMOS, the layout area of the HVPMOS is designed much larger than that of the LDNMOS in the same IC to comply with impedance matching and to match rising time and falling time in response. In general, the LDNMOS having a lower Rdson during operation is usually substituted for the large-scale HVPMOS, that is, a plurality of LDNMOS is included in the PMIC, so as to reduce the layout area of the PMIC chip. However, the source of the LDNMOS which is substituted for the HVPMOS is placed under a relatively high voltage during operation, and therefore, leakage current from the source to the substrate arises due to the difference of electric potential therebetween.